是德科技 EDA 使用者創新峰會

10 月 19 日

General Session：
One Stop Service Solution

Track I：Signal Integrity Design
Embrace the Journey of High-Speed Digital
Overcome DDR Design Challenges
Addressing PAM4 Design Challenges in PCIe6
Understanding the Impact on Parasitic Probing Effects onto the PCB Power-to-Control Crosstalk in Switch-Mode Power Supplies
The Path to Success in Power Integrity Design

Track II：RF and System Level Design
Deploy RF System Architecture, Circuit, and Verification by Innovation Platform
New Touchdown of RF Matching
B5G Era: System Design Challenges and a New Perspective on Simulation
PDK Validation by Version Control and Eggplant Digital Twins